1. Field of the Invention
The present invention relates to a method of driving a plasma display panel.
2. Description of the Related Art
In recent years, a variety of thin display devices have been brought into practical use in response to demands for thinner display devices with the trend of increase in screen sizes thereof. A plasma display panel of AC discharge type has drawn attention as one of thin display devices.
FIG. 1 is a diagram generally illustrating the configuration of a plasma display device which comprises a plasma display panel as mentioned above, and a driver for driving the plasma display panel.
In FIG. 1, a PDP 10 as a plasma display panel comprises m column electrodes D1-Dm as data electrodes, and n each of row electrodes X1-Xn and Y1-Yn which are arranged to intersect with each of the column electrodes. A pair of row electrodes Xi (1xe2x89xa6ixe2x89xa6n) and Yi (1xe2x89xa6ixe2x89xa6n) in these row electrodes X1-Xn and Y1-Yn bear each of display lines on the PDP. These column electrodes D and row electrodes X, Y are disposed in opposition to each other with an intervening discharge space which is filled with a discharge gas, and a discharge cell carrying a pixel is formed at each of intersections of the row electrode pairs and column electrode, including this discharge space. The discharge cell can only take two states, i.e., a xe2x80x9clit statexe2x80x9d and an xe2x80x9cunlit statexe2x80x9d because it emits light through discharge. In other words, the discharge cell only represents two levels of luminance consisting of minimum luminance (unlit state) and maximum luminance (lit state).
A driver 100 performs gradation driving based on a subfield method for the PDP 10 comprising the discharge cells as display cells carrying pixels in order to realize a halftone luminance display corresponding an input video signal. The subfield method involves dividing one field display period into a plurality of subfields, and allocating each of the subfields with a number of times light emission is performed, corresponding to weighting applied to the respective subfields. For example, one field display period is divided into four subfields SF1-SF4, as shown in FIG. 2, which are allocates with the numbers of times of light emission as follows:
SF1: 1
SF2: 2
SF3: 4
SF4: 8
Here, the driver 100 converts an input video signal to 4-bit pixel data corresponding to each pixel. A first to a fourth bit of pixel data correspond to the subfields SF1-SF4, respectively. Then, the subfield method based gradation driving causes discharge cells to emit light the aforementioned numbers of times in the subfields corresponding to the respective bit digits in accordance with a logical level of each bit of the pixel data.
FIG. 3 illustrates a variety of driving pulses applied by the driver 100 to the column electrodes and row electrode pairs of the PDP 10 in each of the subfields for performing the light emission driving as described above, and timings at which the driving pulses are applied.
First, in a simultaneous reset stage Rc shown in FIG. 3, the driver 100 simultaneously applies the row electrodes X1-XN with a reset pulse RPX of positive polarity and the row electrodes Y1-YN with a reset pulse RPY of negative polarity. In response to these reset pulses RPX and RPY, all discharge cells in the PDP 10 are discharged or reset to uniformly form a wall charge of a predetermined amount within the respective discharge cells. In this manner, all the discharge cells in the PDP 10 are once initialized to xe2x80x9clight emitting cells.xe2x80x9d
Next, in an addressing stage Wc, the driver 100 extracts one bit corresponding to this subfield from the 4-bit pixel data as described above, and generates a pixel data pulse having a pulse voltage corresponding to the logical level of the bit. For example, in the subfield SF1, the driver 100 generates a pixel data pulse having a pulse voltage corresponding to the logical level of a first bit of the pixel data. In this event, the driver 100 generates the pixel data pulse having a high voltage pulse when the logical level of the first bit is at xe2x80x9c1xe2x80x9d and a low voltage (zero volt) pulse when at xe2x80x9c0.xe2x80x9d Then, the driver 100 applies one display line of pixel data pulses sequentially to the column electrodes D1-Dm. Specifically, as illustrated in FIG. 3, the driver 100 first applies the column electrodes D1-Dm with a pixel data pulse group DP1 comprised of m pixel data pulses corresponding to a first display line, and next applies the column electrodes D1-Dm with a pixel data pulse group DP2 comprised of m pixel data pulses corresponding to a second display line. Similarly, the driver 100 subsequently applies the column electrodes D1-Dm sequentially with pixel data pulse groups DP3-DPn corresponding to a third to an n-th display line, respectively. The driver 100 further generates a scanning pulse SP of negative polarity in synchronism with the timing at which each pixel data pulse group DP is applied, and sequentially applies the scanning pulse SP to the row electrodes Y1-YN, as illustrated in FIG. 3. In this event, a discharge selectively occurs only in discharge cells at intersections of the display lines applied with the scanning pulse SP with the column electrodes applied with the pixel data pulse at the high voltage (selective erasure discharge), thereby extinguishing the wall charges which have remained in these discharge cells. In this manner, the discharge cells initialized to the xe2x80x9clit discharge cell statexe2x80x9d in the simultaneous reset stage Rc transitions to the xe2x80x9cunlit discharge cell state.xe2x80x9d On the other hand, the selective erasure discharge is not generated in discharge cells which have been applied with the pixel data pulse at the low voltage simultaneously with the scanning pulse SP, so that these cells maintain the state initialized in the simultaneous reset stage Rc, i.e., xe2x80x9clit discharge cell state.xe2x80x9d
In other words, the addressing stage Wc is executed to set each of the discharge cells in the PDP 10 either to the xe2x80x9clit discharge cell statexe2x80x9d or to the xe2x80x9cunlit discharge cell statexe2x80x9d in accordance with the pixel data corresponding to the input video signal.
Next, in a light emission sustain stage Ic, the driver 100 alternately applies the row electrodes X1-Xn and Y1-Yn with sustain pulses IPX and IPY of positive polarity as illustrated in FIG. 3, the number of times allocated to each subfield as mentioned above. In this event, only those discharge cells in which the wall charges remain in the discharge space, i.e., those discharge cells which are in the xe2x80x9clit discharge cell statexe2x80x9d discharge each time they are applied with the sustain pulses IPX and IPY (sustain discharge). In other words, those discharge cells in which the selective erasure discharge was not generated in the addressing stage Wc repeat light emission associated with the sustain discharge the number of times allocated to each subfield as mentioned above to sustain the light emitting state.
Then, in the erasure stage E, the driver 100 applies the row electrodes Y1-Yn with an erasure pulse EP as illustrated in FIG. 3. The application of the erasure pulse EP causes an erasure discharge to be generated in all the discharge cells of the PDP 10, thereby extinguishing the wall charges remaining in the respective discharge cells.
The foregoing sequence of operations comprised of the simultaneous reset stage Rc, addressing stage Wc, light emission sustain stage Ic and erasure stage E is executed in each of the subfields SF1-SF4 shown in FIG. 2. According to the driving as described, light is emitted associated with the sustain discharge number of times corresponding to a luminance level of an input video signal through one field display period to provide visually perceived intermediate luminance in accordance with the number of times of light emission. According to the gradation driving based on the four subfields SF1-SF4 as shown in FIG. 2, it is possible to represent 16 levels of intermediate luminance xe2x80x9c0xe2x80x9d-xe2x80x9c15xe2x80x9d (16 gradational levels).
Here, as one field period is divided into an increased number of subfields, a larger number of gradational levels can be represented to provide a display image of higher quality. For this purpose, the scanning pulse SP and pixel data pulse groups DP illustrated in FIG. 3 are reduced in pulse width to consume a less time for the addressing stage Wc, taking advantage of the resulting extra time to increase the number of subfields.
However, since the scanning pulse SP and pixel data pulse group DP having narrower pulse widths cause the selective discharge, as described above, to be instable, the pulse width cannot be thoughtlessly reduced.
It is an object of the present invention to provide a method of driving a plasma display panel which is capable of displaying a high quality image with an increased number of gradation levels without rendering a selective discharge instable.
A plasma display panel driving method according to the present invention is adapted to drive a plasma display panel in cycles each comprising a plurality of subfields constituting one field of a video signal, the plasma display panel including a plurality of row electrodes corresponding to display lines, a plurality of column electrodes arranged to intersect the row electrodes, and discharge cells each formed at each of intersections of the row electrodes and the column electrodes for carrying a pixel. Each of the subfields includes an addressing stage for sequentially applying each of the column electrodes with one display line of pixel data pulses based on the video signal, and sequentially applying each of the row electrodes with a scanning pulse at the same timing as a timing at which each of the pixel data pulses is applied to selectively discharge each of the discharge cells to set the discharge cell to either a lit discharge cell state or an unlit discharge cell state, and a light emission sustain stage for repeatedly applying each of the row electrodes with a sustain pulse a number of times corresponding to weighting applied to the subfield to cause the discharge cells in the lit discharge cell state to repeatedly discharge such that the discharge cells emit light, wherein the scanning pulse and pixel data pulse applied at an earlier time in the addressing stage in each of the subfields have a narrower pulse width than a pulse width of the scanning pulse and the pixel data pulse which are applied at a later time in the addressing stage.